The present invention generally relates to semiconductor integrated circuits, and more particularly to an on-chip voltage regulator for controlling the generation of an internal power supply voltage from an external power supply voltage.
As the feature scale of LSIs is decreasing, the size of transistors realized by LSIs is reducing, and the breakdown voltages of LSI transistors are decreasing. The are two possible approaches to optimize the relationship between the power supply voltage and the feature scale. The first approach is to produce a transistor having a gate length of approximately 0.8 micrometers which is enough to withstand a high power supply voltage equal to, for example, 5 volts. The second approach is to produce a transistor having a gate length of approximately 0.5 micrometers which is suitable for a decreased power supply voltage equal to, for example, 3.3. volts. It should be noted that the transistor produced by the second approach can operate faster than that produced by the first approach. It is thus concluded that the power supply voltage should be decreased to a suitable voltage as the integration density increases. On the other hand, many IC chips are designed to receive a standardized external power supply voltage equal to 5 volts. Thus, it is necessary to generate a suitably dropped power supply voltage from the standardized external power supply voltage inside of each IC chip.
FIG. 1A is a circuit diagram of a conventional on-chip voltage regulator designed to generate, from an external voltage, an in-chip voltage lower than the external voltage. A regulator transistor Q1 functions as a series control regulator with respect to an external power supply voltage V.sub.EXT equal to, for example, 5 volts. The regulator transistor Q1 generates an internal power supply voltage V.sub.INT equal to, for example, 3.3. volts from the 5.0V external power supply voltage V.sub.EXT. The gate of the regulator transistor Q1 is charged by a voltage obtained by rectifying an A.C. signal generated by a ring oscillator OSC. The gate voltage now labeled V.sub.GI is clamped at a fixed voltage due to the function of a transistor Q4 because the source of the transistor Q4 is set to a reference voltage V.sub.REF. The reference voltage V.sub.REF can be generated by a conventional method, for example, by using the threshold voltage of a MOS transistor.
A transistor Q2 functions to charge the gate of the regulator transistor Q1 when the power supply is turned ON. The reference voltage V.sub.REF is also applied to the gate of the transistor Q2 and the oscillator OSC. The reference voltage V.sub.REF enables the oscillator OSC to generator a fixed oscillation voltage. A capacitor C is connected between the oscillator OSC and the source of the transistor Q2, and functions to increase the charge voltage. For example, when the output voltage of the oscillator OSC is negative, the capacitor C is charged via the transistor Q2 so that the terminal of the C on the side of the transistor Q2 is positive. On the other hand, when the output voltage of the oscillator OSC is positive, the charge voltage is increased so that it becomes equal to the sum of the positive output voltage of the oscillator OSC and the voltage developed across the capacitor C. The oscillator OSC is used for generating the large gate voltage V.sub.G1 of the regulator transistor Q1 in order to obtain the stabilized internal voltage V.sub.INT. The oscillator OSC may be replaced by an alternative device, which oscillates and rectifies a voltage signal so that a peak voltage can be obtained.
FIG. 1B is a drain current (I.sub.D) vs. a gate-source voltage (V.sub.GS) of the regulator transistor Q1. The drain current I.sub.D can be defined as being I.sub.D =k(V.sub.G -Vth).sup.2 where k is a proportional constant, and Vth is the threshold voltage of the regulator transistor Q1. That is, the turn-ON characteristic curve of the regulator transistor Q.sub.1 is proportional to the square of the gate-source voltage V.sub.GS thereof. If current consumed in the chip varies by .DELTA.I, the internal voltage V.sub.INT varies by .DELTA.V. In the case of a DRAM, the current equal to approximately 0.1 mA passes through the regulator transistor Q1 in a standby mode. On the other hand, when an internal circuit of the DRAM is activated, the peak of the current passing through the regulator transistor Q1 becomes approximately equal to 100 mA. That is, the current obtained at the active mode is 1000 times the current obtained in the standby mode. It is possible to increase the gate width to increase the proportional constant k. However, an increase in the gate width decreases the integration density. It can be seen from the above explanation that it is impossible to regulate the internal voltage V.sub.INT at the fixed voltage in the state where the current consumed in the internal circuit is varying. Further, an increase in the gate width leads to an increase in a sub-threshold current, and the threshold voltage of the transistor Q1 is greatly decreased. Thus, if a change in the current consumed in the internal chip is equal to 1000 times that obtained in the standby mode, it causes great variations in the internal voltage V.sub.INT.
FIG. 1C is another conventional on-chip voltage regulator directed to suppressing variations in the internal voltage V.sub.INT. The gate voltage of the regulator transistor Q1 is controlled by an output of a current-mirror type analog differential amplifier, which is composed of transistors Q11-Q14. That is, a feedback signal is applied to the gate of the transistor Q12 from the source of the transistor Q1, that is, a node from which the internal voltage V.sub.INT is output. The reference voltage V.sub.REF is applied to the gate of the transistor Q11. Thus, the internal voltage V.sub.INT is automatically controlled so that it is always equal to the reference voltage V.sub.REF. Thus, the internal voltage V.sub.INT is not greatly affected by variations in a load current, that is, the drain current of the transistor Q1.
Although the voltage stability is good, it is necessary to always pass currents equal to 100 microamperes through the transistors Q11 and Q12 in order to obtain a transfer (amplification) gain necessary for the analog differential amplifier circuit. Thus, a large amount of power is consumed in the circuit shown in FIG. 1C in the standby mode. Further, it is necessary to fabricate the circuit so that the feedback circuit can operate stably. If such a requirement is not satisfied, a ringing will occur in the internal voltage V.sub.INT. In the worst case, the feedback circuit will oscillate.